Physical layout and layout verification of high-performance analog and mixed signal circuits in BICMOS technologies. 

• Learn analog layout implementation flow using Cadence Virtuoso XL
• Transistor level layout of analog specific blocks
• Acquire experience in analog layout matching technique and define block level matching requirements in collaboration with design engineer
• Floor planning, align block level definition with top level requirement
• Layout verification (Design Rule Check, Layout vs. Schematic)
• Understand database structure and revision control system
• Learn about the complete design flow of an IC until mask generation.

Minimum requirements

• Completed 4 or 5 semesters of Bachelor study in Electrical or Computer Engineering. 

Preferred qualifications

• Track record of on-time completion of technical projects
• Experience working in team
• Highly self-motivated with good communication and teamwork skills
• Willing to learn and accomplish tasks independently
• Basic knowledge and understanding of semiconductor technology and electronics
• Experience with LINUX, scripting and programming
• Knowledge of IC layout tools (Cadence IC Design Suite) is strong plus
• Good troubleshooting and debugging skills
• Good English in word and writing, German is a plus as well.