Intern position in the field of ESD (ElectroStatic Discharge) characterization. The intern will join our ESD team at Intel to work in our Munich laboratory to perform Transmission Line Pulse (TLP) testing of most advanced CMOS technology test chips.
As needed, simulations will be carried out to support the measurement data and to get a full understanding of the physical behavior of the structures. The TLP system will also be used to exercise the capability of packaged ICs to handle system level ESD stress (SEED characterization), providing a guidance for system integration.