Pubblicato su stage4eu il: 08/10/2019 Nokia, Trainee, SoC/IP

Karaportti 3, Espoo, Finlandia
Posti disponibili Non specificato
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  • Preparation and review of functional and design specification for SoC/IP
  • RTL or HLS based FPGA design
  • Designing SoC functionality from top-level down to a block level, including low level SW
  • Verification and simulation of needed functionality on the block level
  • Ensuring effective testing and high quality product delivery by advanced SoC verification planning, validation and testing on board
  • Supporting HW/SW Bring-up and debug
  • Co-operation with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues for quality
Requisiti principali:
  • VHDL/Verilog/HLS knowhow for FPGA design
  • Knowledge of SoC (ASIC/FPGA/low level SW) design and verification tools
  • System modeling using Matlab
  • Good knowledge of embedded systems
  • Advanced verification methodologies, e.g. VMM, OVM, UVM
  • LTE and 5G cellular networks and relevant Layer-1 algorithms
  • You are also fluent in spoken and written English.
  • You have high motivation to learn new and work in international teams.
  • You are a good team player.